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Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing…

  MEMS, Lithography, planarization Click Here to Read More

Overcoming spin-coating challenges for square substrates

Process application engineers often encounter a variety of complex challenges related to deposition by spin coating, as many variables affect the quality of the spin-applied coating. These variables have critical effects on the overall coating uniformity, coating thickness, and subsequent device yield. Some of the more influential variables that must be controlled precisely are spin…

  Wafer-Level packaging, coat uniformity, spin coat, spin process, square substrate Click Here to Read More

Thermally curable middle layer for 193-nm trilayer resist process

New lithographic compositions, for use as middle layers in trilayer processes  resist processes can be applied as very thin films with a very thin layer of photoresist being applied to the top of the middle layer. Thus, the underlying bottom anti-reflective coating is still protected even though the overall stack (i.e., anti-reflective coating plus middle…

  trilayer, trilayer resist process, lithographic, lithographic composition, anti-reflective coating, 193-nm, unilayer processing, depth-of-focus, Lithography Click Here to Read More

High-k metal gate (HKMG) technology for CMOS devices

High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves the dielectric constant. To help with fermi-level pinning and to allow the gate to be adjusted to low threshold voltages, a metal gate is used…

  other Click Here to Read More

Controlling the spin bowl environment to optimize spin coat quality

A variety of factors can affect the coat quality when spin processing. This article will focus on the role that the bowl environment, and in particlar the ability to control the fume exhaust, has on this process. The drying rate of the resin fluid during the spin process is defined by the nature of the…

  other, spincoat, coat uniformity, spin coat, spin process, spin bowl Click Here to Read More

Solvent vapor control for optimal thick-film spin coating

One of the most critical variables in spin-coating processes is coating uniformity. In many cases, engineers are challenged with achieving ultralow total thickness variation at high film thicknesses while conserving expensive materials. To achieve such a highly uniform coating, automated control of the solvent vapors is essential. A closed bowl environment combined with a programmable…

  Wafer-Level packaging, coat uniformity, thick-film, spin coat Click Here to Read More

Background of multilayer processing

As semiconductor devices evolve, smaller and smaller feature sizes are required to achieve the performance desired by the consumer. Smaller features give rise to lower power consumption for mobile devices, less expensive devices due to the ability to manufacture more chips per wafer, and faster overall speed.  Why multilayer? Smaller feature sizes also lead to…

  Multilayer, Lithography Click Here to Read More

Jim Lamb at Science Cafe

At the Science Café event held at Farmers Gastropub on April 19, James E. (Jim) Lamb III, Brewer Science Corporate Technology Strategist and Director of the Printed Electronics Technology Center, spoke to the Springfield, MO, community about printed electronics and what we can expect to see in the future. His interesting and informative presentation described…

  Community, Education, company, unplugged Click Here to Read More

Processing wafers with high-topography 3-D structures

Over the past decade, Brewer Science has developed and published various methods of creating a planar surface over three-dimensional (3-D) structures. Sharing these results invariably leads to a potential customer asking, “Can you fill the holes in my substrate that are x in size?” The short answer to the question is “Yes, we can.” Filling…

  TSV, Wafer-Level packaging, planarization Click Here to Read More

Bake plate enhancements for optimal thick-film curing results

High-uniformity bake plates have been displacing convection ovens for well over two decades in the microelectronics industry. The disadvantages of variable temperature zones, lengthened cure times, and considerable particle contamination have been thoroughly analyzed and confirmed. Although temperature uniformity remains the primary advantage for precision hot plates, virtually eliminating skinning effects for thin-film (< 1-5…

  other, coat uniformity, thick-film Click Here to Read More
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