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Directed Self-Assembly

 Directed self-assembly (DSA) refers to the integration of block copolymer (BCP) materials that undergo phase separation with traditional manufacturing processes. With DSA, nanoscale dimensions are achieved at a drastically reduced cost by novel material designs without additional equipment upgrades. Alternative lithographic approaches to achieve features ≤10 nanometers in size typically involve higher equipment budgets or…

  Lithography Click Here to Read More

Directed Self-Assembly: From the Top-Down to the Bottom-Up

In previous posts, we’ve made references to Moore’s law and how, with uncanny accuracy, it has predicted that the number of transistors in a dense integrated circuit (IC) would double approximately every two years. The semiconductor industry has tirelessly chased Moore's law ever since it was first coined in the 1970s, but as ICs have…

  Directed Self-Assembly, Lithography, DSA, Integrated Circuits Click Here to Read More

3 places where solar energy is having a tremendous impact

For centuries, humans have tried to harness the seemingly endless power of the sun. And now, it seems like we’re making some big strides. Here are just a few amazing places where solar is really shining. Up on the roof Perhaps the roof isn’t an unlikely place for solar panels to live. Maybe it even…

  solar energy Click Here to Read More

Lithography process simplification for reduced cost of ownership

Cost of ownership plays an important role in lithography process materials and methods decisions. Process simplifications brought about by layer-to-layer synergy drive significant cost of ownership advantages for multilayer lithography systems such as the Brewer Science® OptiStack® system. Savings in mask engineering and manufacture are the greatest cost difference. Optical proximity correction (OPC) algorithms need…

  Lithography, EUV, Multilayer Click Here to Read More

Supply chain flexibility for 3D device packaging

Limitations of Moore's Law Ultimately, performance of computers and other electronic products will be limited by transistor size and density. Because the semiconductor industry has pushed to create ever-smaller features with photolithography, engineers have been able to shrink transistors far beyond original expectations to dramatically increase the density of transistors on a chip, thereby enabling…

  supply chain, 3D packaging Click Here to Read More

Planarization: Leveling extreme topography for microelectronics

Fabrication of microelectronic devices increasingly involves the creation of high-aspect-ratio structures (those with large height or depth and narrow width, such as trenches, vias, columns, and mesas).  These structures provide isolation; serve as conduits for electrical, optical, or fluid signals; or enable pre-dicing before die singulation. New designs in semiconductor and MEMS devices are pushing…

  MEMS, Lithography, planarization Click Here to Read More

Overcoming spin-coating challenges for square substrates

Process application engineers often encounter a variety of complex challenges related to deposition by spin coating, as many variables affect the quality of the spin-applied coating. These variables have critical effects on the overall coating uniformity, coating thickness, and subsequent device yield. Some of the more influential variables that must be controlled precisely are spin…

  Wafer-Level packaging, coat uniformity, spin coat, spin process, square substrate Click Here to Read More

Thermally curable middle layer for 193-nm trilayer resist process

New lithographic compositions, for use as middle layers in trilayer processes  resist processes can be applied as very thin films with a very thin layer of photoresist being applied to the top of the middle layer. Thus, the underlying bottom anti-reflective coating is still protected even though the overall stack (i.e., anti-reflective coating plus middle…

  trilayer, trilayer resist process, lithographic, lithographic composition, anti-reflective coating, 193-nm, unilayer processing, depth-of-focus, Lithography Click Here to Read More

High-k metal gate (HKMG) technology for CMOS devices

High-k metal gate (HKMG) technology has become one of the front-runners for the next generation of CMOS devices. This new technology incorporates a high-k dielectric, which reduces leakage and improves the dielectric constant. To help with fermi-level pinning and to allow the gate to be adjusted to low threshold voltages, a metal gate is used…

  other Click Here to Read More

Controlling the spin bowl environment to optimize spin coat quality

A variety of factors can affect the coat quality when spin processing. This article will focus on the role that the bowl environment, and in particlar the ability to control the fume exhaust, has on this process. The drying rate of the resin fluid during the spin process is defined by the nature of the…

  other, spincoat, coat uniformity, spin coat, spin process, spin bowl Click Here to Read More
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